ST20CX 查看數據表（PDF） - STMicroelectronics

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ST20CX

Instruction Set Reference Manual

STMicroelectronics 

clockdis

clockdis

clock disable

Code: 64 FE

Description: Stops the clocks specified in bits 0 and 1 of Areg where bit 0 indicates

the high priority clock and bit 1 the low priority clock. The original values of these two

clock enable bits are returned in Areg.

Definition:

Areg′ 1..0 ← ClockEnables

Areg′31..2

←0

ClockEnables′ ← ClockEnables ∧ ∼Areg

Error signals: none

Comments:

Secondary instruction.

See also: clockenb

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