ST72521AR6T6 查看數據表（PDF） - STMicroelectronics

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ST72521AR6T6

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521

12.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi-

mum ratings” may cause permanent damage to

the device. This is a stress rating only and func-

tional operation of the device under these condi-

12.2.1 Voltage Characteristics

tions is not implied. Exposure to maximum rating

conditions for extended periods may affect device

reliability.

Symbol

Ratings

VDD - VSS

VPP - VSS

VIN 1) & 2)

Supply voltage

Programming Voltage

Input Voltage on true open drain pin

Input voltage on any other pin

|∆VDDx| and |∆VSSx| Variations between different digital power pins

|VSSA - VSSx|

Variations between digital and analog ground pins

VESD(HBM)

Electro-static discharge voltage (Human Body Model)

VESD(MM)

Electro-static discharge voltage (Machine Model)

12.2.2 Current Characteristics

Maximum value

6.5

13

VSS-0.3 to 6.5

VSS-0.3 to VDD+0.3

50

50

Unit

V

mV

see Section 12.7.3 on page 179

Symbol

Ratings

Maximum value

Unit

IVDD

IVSS

Total current into VDD power lines (source) 3)

Total current out of VSS ground lines (sink) 3)

150

mA

150

Output current sunk by any standard I/O and control pin

25

IIO

Output current sunk by any high sink I/O pin

50

Output current source by any I/Os and control pin

- 25

IINJ(PIN) 2) & 4)

Injected current on VPP pin

Injected current on RESET pin

Injected current on OSC1 and OSC2 pins

±5

mA

±2

±5

Injected current on any other pin 5) & 6)

±5

ΣIINJ(PIN) 2)

Total injected current (sum of all I/O and control pins) 5)

± 25

Notes:

1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset

is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).

To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for

RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS.

2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to

IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.

3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.

4. Negative injection disturbs the analog performance of the device. See note in “ADC Accuracy” on page 194.

For best reliability, it is recommended to avoid negative injection of more than 1.6mA.

5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive

and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi-

mum current injection on four I/O port pins of the device.

6. True open drain I/O port pins do not accept positive injection.

163/211

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