ST72F521R9TC 查看數據表（PDF） - STMicroelectronics

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ST72F521R9TC

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521

OPERATING CONDITIONS (Cont’d)

12.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for VDD, fCPU, and TA.

Symbol

VIT+(LVD)

VIT-(LVD)

Vhys(LVD)

VtPOR

tg(VDD)

Parameter

Reset release threshold

(VDD rise)

Reset generation threshold

(VDD fall)

LVD voltage threshold hysteresis 1)

VDD rise time 1)2)

VDD glitches filtered (not detected)

by LVD 1)

Conditions

Min

VD level = High in option byte 4.0 1)

VD level = Med. in option byte3) 3.55 1)

VD level = Low in option byte3) 2.95 1)

VD level = High in option byte 3.8

VD level = Med. in option byte3) 3.351)

VD level = Low in option byte3) 2.81)

VIT+(LVD)-VIT-(LVD)

150

6

Typ

4.2

3.75

3.15

4.0

3.55

3.0

200

Max

4.5

4.01)

3.351)

4.25 1)

3.751)

3.15 1)

250

∝

40

Unit

V

mV

µs/V

ns

Notes:

1. Data based on characterization results, not tested in production.

2. When VtPOR is faster than 100 µs/V, the Reset signal is released after a delay of max. 42µs after VDD crosses the

VIT+(LVD) threshold.

3. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range.

Below 3.8V, device operation is not guaranteed.

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