ST7PMC2R7T6(2004) 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

ST7PMC2R7T6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

SCICR2 register is set, the LHDM bit selects the

Wake-Up method (replacing the WAKE bit).

0: LIN Synch Break Detection Method

1: LIN Identifier Field Detection Method

Figure 70. LSF bit set and clear

11 dominant bits

parity bits

Bit 2 = LHIE LIN Header Interrupt Enable

This bit is set and cleared by software. It is only us-

able in LIN Slave mode.

0: LIN Header Interrupt is inhibited.

1: An SCI interrupt is generated whenever

LHDF=1.

Bit 1= LHDF LIN Header Detection Flag

This bit is set by hardware when a LIN Header is

detected and cleared by a software sequence (an

access to the SCISR register followed by a read of

the SCICR3 register). It is only usable in LIN Slave

mode.

0: No LIN Header detected.

1: LIN Header detected.

Notes: The header detection method depends on

the LHDM bit:

– If LHDM=0, a header is detected as a LIN

Synch Break.

– If LHDM=1, a header is detected as a LIN

Identifier, meaning that a LIN Synch Break

Field + a LIN Synch Field + a LIN Identifier

Field have been consecutively received.

Bit 0= LSF LIN Synch Field State

This bit indicates that the LIN Synch Field is being

analyzed. It is only used in LIN Slave mode. In

Auto Synchronization Mode (LASE bit=1), when

the SCI is in the LIN Synch Field State it waits or

counts the falling edges on the RDI line.

It is set by hardware as soon as a LIN Synch Break

is detected and cleared by hardware when the LIN

Synch Field analysis is finished (See Figure 70).

This bit can also be cleared by software to exit LIN

Synch State and return to idle mode.

0: The current character is not the LIN Synch Field

1: LIN Synch Field State (LIN Synch Field under-

going analysis)

LSF bit

LIN Synch LIN Synch Identifier

Break

Field

Field

LIN DIVIDER REGISTERS

LDIV is coded using the two registers LPR and LP-

FR. In LIN Slave mode, the LPR register is acces-

sible at the address of the SCIBRR register and

the LPFR register is accessible at the address of

the SCIETPR register.

LIN PRESCALER REGISTER (LPR)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

LPR7 LPR6 LPR5 LPR4 LPR3 LPR2 LPR1 LPR0

LPR[7:0] LIN Prescaler (mantissa of LDIV)

These 8 bits define the value of the mantissa of the

LIN Divider (LDIV):

LPR[7:0]

00h

01h

...

FEh

FFh

Rounded Mantissa (LDIV)

SCI clock disabled

1

...

254

255

Caution: LPR and LPFR registers have different

meanings when reading or writing to them. Conse-

quently bit manipulation instructions (BRES or

BSET) should never be used to modify the

LPR[7:0] bits, or the LPFR[3:0] bits.

130/294

1

Share Link: