ST7FMC1M2T3 查看數據表（PDF） - STMicroelectronics

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ST7FMC1M2T3

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

BAUD RATE REGISTER (SCIBRR)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

Note: When LIN slave mode is disabled, the SCI-

BRR register controls the conventional baud rate

generator.

Bits 7:6 = SCP[1:0] First SCI Prescaler

These 2 prescaling bits allow several standard

clock division ranges:

PR Prescaling factor

1

3

4

13

SCP1

0

1

SCP0

0

1

0

1

Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 and

SCP0 bits define the total division applied to the

bus clock to yield the transmit rate clock in conven-

tional Baud Rate Generator mode.

TR dividing factor

1

2

4

8

16

32

64

128

SCT2

0

1

SCT1

0

1

0

1

SCT0

0

1

0

1

0

1

0

1

Bits 2:0 = SCR[2:0] SCI Receiver rate divider

These 3 bits, in conjunction with the SCP[1:0] bits

define the total division applied to the bus clock to

yield the receive rate clock in conventional Baud

Rate Generator mode.

RR dividing factor

1

2

4

8

16

32

64

128

SCR2

0

1

SCR1

0

1

0

1

SCR0

0

1

0

1

0

1

0

1

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