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ST7MC2N6 查看數據表(PDF) - STMicroelectronics

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ST7MC2N6 Datasheet PDF : 309 Pages
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ST7MC1xx/ST7MC2xx
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 148. SPI Slave Timing Diagram with CPHA=11)
SS INPUT
tsu(SS)
tc(SCK)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO)
MISO OUTPUT
see
note 2
HZ
tsu(SI)
MSB OUT
th(SI)
BIT6 OUT
th(SS)
th(SO)
tr(SCK)
tf(SCK)
LSB OUT
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Figure 149. SPI Master Timing Diagram 1)
tdis(SO)
see
note 2
SS INPUT
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
MISO INPUT
tc(SCK)
tsu(MI)
th(MI)
ttww((SSCCKKLH))
MSB IN
tv(MO)
BIT6 IN
MOSI OUTPUT See note 2
MSB OUT
BIT6 OUT
tr(SCK)
tf(SCK)
th(MO)
LSB IN
LSB OUT
See note 2
Notes:
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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