ST7MC2N6T3 查看數據表（PDF） - STMicroelectronics

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ST7MC2N6T3

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.3.3 Clock Security System (CSS)

The Clock Security System (CSS) protects the

ST7 against main clock problems. To allow the in-

tegration of the security features in the applica-

tions, it is based on a PLL which can provide a

backup clock. The PLL can be enabled or disabled

by option byte or by software. It requires an 8-MHz

input clock and provides a 16-MHz output clock.

6.3.3.1 Safe Oscillator Control

The safe oscillator of the CSS block is made of a

PLL.

If the clock signal disappears (due to a broken or

disconnected resonator...) the PLL continues to

provide a lower frequency, which allows the ST7 to

perform some rescue operations.

Note: The clock signal must be present at start-up.

Otherwise, the ST7MC will not start and will be

maintained in RESET conditions.

6.3.3.2 Limitation detection

The automatic safe oscillator selection is notified

by hardware setting the CSSD bit of the SICSR

register. An interrupt can be generated if the CS-

SIE bit has been previously set.

These two bits are described in the SICSR register

description.

6.3.4 Low Power Modes

Mode

Wait

Halt

Description

No effect on SI. CSS and AVD interrupts

cause the device to exit from Wait mode.

The CRSR register is frozen.

The CSS (including the safe oscillator) is

disabled until Halt mode is exited. The pre-

vious CSS configuration resumes when the

MCU is woken up by an interrupt with “exit

from Halt mode” capability or from the coun-

ter reset value when the MCU is woken up

by a RESET. The AVD remains active, and

an AVD interrupt can be used to exit from

Halt mode.

6.3.4.1 Interrupts

The CSS or AVD interrupt events generate an in-

terrupt if the corresponding Enable Control Bit

(CSSIE or AVDIE) is set and the interrupt mask in

the CC register is reset (RIM instruction).

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

CSS event detection

(safe oscillator acti- CSSD CSSIE Yes

vated as main clock)

AVD event

AVDF AVDIE Yes

Exit

from

Halt

No 1)

Yes

Note 1: This interrupt allows to exit from Active-

halt mode.

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