ST7FMC1M7T3 查看數據表（PDF） - STMicroelectronics

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ST7FMC1M7T3

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

I/O PORTS (Cont’d)

CAUTION: The alternate function must not be ac-

tivated as long as the pin is configured as input

with interrupt, in order to avoid generating spurious

interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O

must be configured as floating input. The analog

multiplexer (controlled by the ADC registers)

switches the analog voltage present on the select-

ed pin to the common analog rail which is connect-

ed to the ADC input.

It is recommended not to change the voltage level

or loading on any port pin while conversion is in

progress. Furthermore it is recommended not to

have clocking pins located close to a selected an-

alog pin.

WARNING: The analog input voltage level must

be within the limits stated in the absolute maxi-

mum ratings.

9.3 I/O PORT IMPLEMENTATION

The hardware implementation on each I/O port de-

pends on the settings in the DDR and OR registers

and specific feature of the I/O port such as ADC In-

put or true open drain.

Switching these I/O ports from one state to anoth-

er should be done in a sequence that prevents un-

wanted side effects. Recommended safe transi-

tions are illustrated in Figure 33 on page 57. Other

transitions are potentially risky and should be

avoided, since they are likely to present unwanted

side-effects such as spurious interrupt generation.

Figure 33. Interrupt I/O Port State Transitions

01

00

INPUT

floating/pull-up

interrupt

INPUT

floating

(reset state)

10

OUTPUT

open-drain

11

OUTPUT

push-pull

XX = DDR, OR

9.4 LOW POWER MODES

Mode

Wait

Halt

Description

No effect on I/O ports. External interrupts

cause the device to exit from Wait mode.

No effect on I/O ports. External interrupts

cause the device to exit from Halt mode.

9.5 INTERRUPTS

The external interrupt event generates an interrupt

if the corresponding configuration is selected with

DDR and OR registers and the interrupt mask in

the CC register is not active (RIM instruction).

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

External interrupt on

selected external

-

event

DDRx

ORx

Yes

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