ST92195D7 查看數據表（PDF） - STMicroelectronics

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ST92195D7

48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER

STMicroelectronics 

ST92195C/D - VOLTAGE SYNTHESIS TUNING CONVERTER (VS)

VOLTAGE SYNTHESIS (Cont’d)

PWM Generation

The counter increments continuously, clocked at

INTCLK divided by 4. Whenever the 7 least signif-

icant bits of the counter overflow, the VS output is

set.

The state of the PWM counter is continuously

compared to the value programmed in the 7 most

significant bits of the tuning word. When a match

occurs, the output is reset thus generating the

PWM output signal on the VS pin.

This Pulse Width modulated signal must be fil-

tered, using an external RC network placed as

close as possible to the associated pin. This pro-

vides an analog voltage proportional to the aver-

age charge passed to the external capacitor. Thus

for a higher mark/space ratio (High time much

Figure 108. PWM Generation

greater than Low time) the average output voltage

is higher. The external components of the RC net-

work should be selected for the filtering level re-

quired for control of the system variable.

Figure 107. Typical PWM Output Filter

PWM OUT

1K

Rext

OUTPUT

VOLTAGE

Cext

COUNTER

127

7-BIT PWM

VALUE

OVERFLOW

OVERFLOW

OVERFLOW

000

t

PWM OUTPUT

t

INTCLK/4 x 128

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