STLC5412 查看數據表（PDF） - STMicroelectronics
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STLC5412 Datasheet PDF : 74 Pages
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STLC5412
Data is transmitted in both directions at half the
data clock rate. The information is clocked by the
transmitter on the front edge of the data clock and
can be accepted by the receiver after 1 to 1.5 pe-
riod of the data clock.
The data clock (BCLK) is a square wave signal at
twice the data transmission frequency on Bx and
Br with a 1 to 1 duty cycle. The frequency can be
choosen from 512 to 6176 kHz with 16 kHz
modularity. Data transmission rate depends only
on the data clock rate.
Table 1: GCI Configuration selection.
The Frame Clock FSa is a 8 kHz signal for syn-
chronization of data transmission. The front edge
of this signal gives the time reference of the first
bit in the first GCI input and output channel, and
reset the slot counter at the start of each frame.
When some GCI channels are not selected on
devices connected to the same GCI link, these
time slots are free for alternative uses.
GCI configuration selection is done by biasing of
input pins MW, M0, CONF1, CONF2 according to
Table 1.
Pin Number
PLCC44 DIP28
Pin name
LT/NT12 (1)
43
28
MW
0
42
27
M0
0
27
19
S1/CONF1
S1
25
17
S2/CONF2
S2
10
7 S0/FSb/TEST2
S0
26
18
IO1/ES1 (2)
IO1
24
16
IO2/ES2 (2)
IO2
NT/TE
0
1
0
1
FSb
IO1
IO2
Configuration
NT1-AUTO LT-RR-AUTO NT-RR-AUTO
0
0
0
1
1
1
1
1
0
1
0
0
TEST2
TEST2
TEST2
ES1
PLDD
ES1
ES2
EC
ES2
23
15
IO3/EC (2)
IO3
22
14 IO4/TEST1 (2)
IO4
35
22 SFSx/RFS (2)
SFSx
IO3
IO4
SFSx
EC
TEST1
SFSx
LFS
TEST1
RFS
LFS
TEST1
RFS
(1) Differentation between LT and NT configuration done by bit NTS in CR2 register; GCI in slave mode.
When NT1-AUTO or NT-RR-AUTO configuration is selected, BCLK bit clock frequency of 512 kHz is
automatically selected
When NT configuration is selected, BCLK bit clock frequency of 1536 kHz is automatically selected.
(2) Connected to VCC through internal pull-up resistors.
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