STLC5412 查看數據表（PDF） - STMicroelectronics

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STLC5412

2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE

STMicroelectronics 

STLC5412

area 00/0FH: NOP operations.

area 10/1FH: test registers: reserved.

area 20/2FH: the configuration registers.

OPR CR1 CR2 CR3 CR4 CR5

CR6 CR7

Read Write access. CR5 only

usefull in GCI mode

area 30/3FH: the B1 B2 D time slot registers.

TXB1 TXB2 RXB1 RXB2 TXD

RXD STATUS

Read Write access except

STATUS: Read only.

Usefull only in µW mode

except STATUS: µW & GCI

modes.

area 40/4FH: the transmit and receive

registers (except EOC).

TXM4 RXM4 TXM56 RXM56

TXACT RXACT BEC1 BEC2

ECT1 ECT2 RXOH

Read Write access for the

transmit registers:

TXM4 TXM56 TXACT

Read access only for the

receive registers:

RXM4 RXM56 RXACT

Read Write access for the

control registers:

ECT1 ECT2

Read access only for the error

registers:

BEC1 BEC2

Write access only for the

command registers:

RXOH

area 5x to Bx:

5x:

6x:

7x:

8x & 9x:

Ax:

Bx:

area C0/C3H:

areaC4HtoEx:

area Fx:

for 12 bits registers.

to write TXEOC register, to read

RXEOC register.

to read TXEOC register.

reserved

to read IDR register.

to write DECTEOC register

to read DECTEOC register

to read round trip delay registers

reserved

reserved except FF address:

special register MWPS.

Overhead bits Programmable Register (OPR)

After reset: 1EH

CIE EIE FIE OB1 OB0 OC1 OC0 C2E

CIE Near-End CRC Interrupt Enable:

CIE = 1:

the RXM56 register is queued in the

interrupt register stack with nebe bit

set to zero each time the CRC result

is not identical to the corresponding

CRC received from the line.

CIE = 0: no interrupt is issued but the error

detection remains active for instance

for on chip error counting.

EIE Error counting Interrupt Enable:

EIE = 1: an interrupt is provided for the

counter when the threshold (ECT1 or

ECT2) is reached.

EIE= 0: no interrupt is issued. It is feasible to

read the counters even if no relevant

interrupt has been provided.

FIE FEBE lnterrupt Enable:

FIE = 1:

FIE = 0:

the RXM56 register is queued into

the interrupt register stack each time

the febe bit is received at zero in a

superframe.

no interrupt is issued but the receive

febe bit remains active for on chip

error counting.

OB1, OB0 Overhead Bit processing:

select how each spare overhead bit received from

the line is validated and transmitted to the sys-

tem. RXM4 and RXM56 registers are inde-

pendently provided onto the system interface as

for the eoc channel. Each spare overhead bit is

validated independentlyfrom the others.

OB1

0

0

1

1

OB0

0

1

0

1

each super frame, an interrupt

is generated for the RXM4 or

the RXM56 register. Spare bits

are transparently transmited to

the system.

an interrupt is set at each new

spare overhead bit(s) received.

an interrupt is set at each new

spare overhead bit(s) received

and confirmed once. ( two

times identical).

an interrupt is set at each new

spare overhead bit(s) received

and confirmed twice. (three

times identical).

If new bits are received at the same time in M4

42/74

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