STPIC44L02PTR 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

STPIC44L02PTR

4 CHANNEL SERIAL AND PARALLEL LOW SIDE PRE-FET DRIVER

STMicroelectronics 

STPIC44L02

Figure 8 : SDO Switching Time

Figure 9 : FLT Switching Time

PRINCIPLES OF OPERATION

SERIAL DATA OPERATION

The STPIC44L02 offers serial input interface to

the microcontroller to transfer control data to the

predriver and fault data back to the controller. The

serial input interface consists of:

SCLK - Serial Clock

CS - Chip Select

SDI - Serial Data Input

SDO - SeriaL Data Output

Serial data is shifted into the least significant bit

(LSB) of the SDI shift register on the rising edge of

the first SCLK after CS has transitated from 1 to 0.

The CS must be transitated from 1 to 0 before the

falling edge of the first clock (see note 1).

Four clock cycles must occur before CS

transitates high for a proper control of the outputs.

Less than four clock cycles result in fault data

being latched into the output control buffer.

Eight bits data can be shifted into the device, but

the first 4 bits shifted out are always the fault data

and the last 4 bits shifted in are always the output

control data. A low-to-high transition on CS

latches the contents of the serial shift register into

the output control register. A logic 0 input to SDI

turns off the corresponding parallel output and a

logic 1 input turns the output on (see figure 10).

Data is shifted out of SDO on the falling edge of

SCLK. The MSB of fault data is available after CS

is transitated low. The remaining 3 bits of fault

data are shifted out in the following three clock

cycles. Fault data is latched into the serial register

when CS is transitated low. A fault must be

present on the high to low transition of CS to be

captured by the device. The CS input must be

transitated to a high state after the last bit of serial

data has been clocked into the device. The rising

edge of CS inhibit SDI puts SDO into a high

impedance state, latches the 4 bits of serial data

into the output control register, and clears and

reenables the serial fault registers (see figure 11).

When a shorted load condition occurs, the device

automatically retries the output and the fault clears

after the fault condition has been corrected.

10/21

Share Link: