QL6500-4PS672M 查看數據表（PDF） - QuickLogic Corporation

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QL6500-4PS672M

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

Eclipse Family Data Sheet Rev. F

JTAG Pin Descriptions

Table 7: JTAG Pin Descriptions

Pin

Function

TDI/RSI

Test Data In for JTAG/RAM init.

Serial Data In

TRSTB/RRO

Active low Reset for JTAG/RAM

init. reset out

TMS

Test Mode Select for JTAG

TCK

TDO/RCO

Test Clock for JTAG

Test data out for JTAG/RAM init.

clock out

Description

Hold HIGH during normal operation. Connects to serial PROM

data in for RAM initialization. Connect to VCC if unused

Hold LOW during normal operation. Connects to serial PROM

reset for RAM initialization. Connect to GND if unused

Hold HIGH during normal operation. Connect to VCC if not used for

JTAG

Hold HIGH or LOW during normal operation. Connect to VCC or

ground if not used for JTAG

Connect to serial PROM clock for RAM initialization. Must be left

unconnected if not used for JTAG or RAM initialization

NOTE: All JTAG inputs are clamped to the VCC rail, not the VCCIO. Therefore, these pins can only be driven

up to VCC + 0.3 V. These input pins are LVCMOS2 compliant only (2.5 V). All JTAG outputs are driven by the

VCC rail, not VCCIO. Therefore, these output pins can only drive up to VCC + 0.3 V. These output pins are

LVCMOS2 compliant only (2.5 V).

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