QL6500-4PS672M 查看數據表（PDF） - QuickLogic Corporation

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QL6500-4PS672M

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

WCLK

Eclipse Family Data Sheet Rev. F

Figure 23: RAM Cell Synchronous Write Timing

WA

WD

WE

RD

tSWA

tHWA

tSWD

tHWD

tSWE

old data

tHWE

tWCRD

new data

Table 16: RAM Cell Synchronous and Asynchronous Read Timing

Symbol

Parameter

RAM Cell Synchronous Read Timing

tSRA

RA setup time to RCLK: time the READ ADDRESS must be stable before the

active edge of the READ CLOCK

tHRA

RA hold time to RCLK: time the READ ADDRESS must be stable after the active

edge of the READ CLOCK

tSRE

RE setup time to WCLK: time the READ ENABLE must be stable before the active

edge of the READ CLOCK

tHRE

RE hold time to WCLK: time the READ ENABLE must be stable after the active

edge of the READ CLOCK

tRCRD

RCLK to RD: time between the active READ CLOCK edge and the time when the

data is available at RD

RAM Cell Asynchronous Read Timing

rPDRD

RA to RD: time between when the READ ADDRESS is input and when the DATA

is output

Value

Min.

Max.

0.686 ns

-

0 ns

-

0.243 ns

-

0 ns

-

-

2.225 ns

-

2.405 ns

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www.quicklogic.com

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