AT/TSC8x251G2D
Table 28. Summary of Exchange, Push and Pop Instructions
Exchange bytesXCH A, <src>(A) ↔ src opnd
Exchange DigitXCHD A, <src>(A)3:0 ↔ src opnd3:0
PushPUSH <src>(SP) ← (SP) +1; ((SP)) ← src opnd;
(SP) ← (SP) + size (src opnd) - 1
PopPOP <dest>(SP) ← (SP) - size (dest opnd) + 1;
dest opnd ← ((SP)); (SP) ← (SP) -1
Mnemonic
<dest>,
<src>(1)
Comments
Binary Mode Source Mode
Bytes States Bytes States
A, Rn
ACC and register
1
3
2
4
XCH
A, dir8
ACC and direct address (on-chip
RAM or SFR)
2
3(3)
2
3(3)
A, at Ri
ACC and indirect address
1
4
2
5
XCHD
A, at Ri
dir8
ACC low nibble and indirect address
(256 bytes)
1
4
2
5
Push direct address onto stack
2
2(2)
2
2(2)
#data
Push immediate data onto stack
4
4
3
3
PUSH
#data16
Rm
Push 16-bit immediate data onto
stack
Push byte register onto stack
5
5
4
5
3
4
2
3
WRj
Push word register onto stack
3
5
2
4
DRk
Push double word register onto
stack
3
9
2
8
dir8
Pop direct address (on-chip RAM or
SFR) from stack
2
3(2)
2
3(2)
POP
Rm
Pop byte register from stack
WRj
Pop word register from stack
3
3
2
2
3
5
2
4
DRk
Pop double word register from stack
3
9
2
8
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.
Add 3 if it addresses a Peripheral SFR.
35
4135F–8051–11/06