AT80251G2D-3CSUM(2006) 查看數據表（PDF） - Atmel Corporation

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AT80251G2D-3CSUM
(Rev.:2006)

8/16-bit Microcontroller with Serial Communication Interfaces

Atmel Corporation 

Verify Algorithm

4135F–8051–11/06

AT/TSC8x251G2D

• PSEN# and the other control signals have to be released to complete a sequence of

programming operations or a sequence of programming and verifying operations.

Figure 6. Setup for Programming

VDD

VDD

VPP

100 ms pulses

Mode

RST

EA#/VPP

ALE/PROG#

PSEN#

VDD

TSC87251G2D

P0[7:0]

A[7:0]

A[14:8]

Data

P3[7:0]

P1[7:0]

XTAL1

VSS/VSS1/VSS2

P2[7:0]

4 to 12 MHz

Table 36. Programming Modes

ROM Area(1)

PSEN

RST EA#/VPP

#

ALE/PROG#(2) P0

P2 P1(MSB) P3(LSB)

On-chip Code

Memory

1

VPP

0

1 Pulse

16-bit Address

68h Data 0000h-7FFFh (32

kilobytes)

Configuration

Bytes

1

VPP

0

1 Pulse

69h

Data

CONFIG0: FFF8h

CONFIG1: FFF9h

Lock Bits

1

VPP

0

1 Pulse

LB0: 0001h

6Bh

X LB1: 0002h

LB2: 0003h

Encryption Array 1

VPP

0

1 Pulse

6Ch Data 0000h-007Fh

Notes: 1. Signature Bytes are not user-programmable.

2. The ALE/PROG# pulse waveform is shown in Figure 23 page 59.

Figure 7 shows the hardware setup needed to verify the TSC87251G2D

EPROM/OTPROM or TSC83251G2D ROM areas:

• The chip has to be put under reset and maintained in this state until the completion

of the verifying sequence.

• PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.

• Then PSEN# has to be to forced to a low level after two clock cycles or more and it

has to be maintained in this state until the completion of the verifying sequence (see

below).

• The voltage on the EA# pin must be set to VDD and ALE must be set to a high level.

• The Verifying Mode is selected according to the code applied on Port 0. It has to be

applied until the completion of this verifying operation.

• The verifying address is applied on Ports 1 and 3 which are respectively the MSB

and the LSB of the address.

43

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