XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
4.3.1
Low power data registers (h0000-h0007)
Name
Address
7
6
5
4
3
2
1
0
Reg00
h0000
Reg00[7:0]
rw, 00000000, glob
Reg01
h0001
Reg01[7:0]
rw,00000000,glob
Reg02
h0002
Reg02[7:0]
rw,00000000,glob
Reg03
h0003
Reg03[7:0]
rw,00000000,glob
Reg04
h0004
Reg04[7:0]
rw,00000000,glob
Reg05
h0005
Reg05[7:0]
rw,00000000,glob
Reg06
h0006
Reg06[7:0]
rw,00000000,glob
Reg07
h0007
Reg07[/:0]
rw,0000000,glob
Table 4-4-3. Low power data registers
4.3.2
System, clock configuration and reset configuration (h0010-h001F)
Name
Address
7
RegSysCtrl SleepEn
h0010
rw,0,cold
RegSysReset Sleep
h0011
rw,0,glob
RegSysClock CpuSel
h0012
rw,0,sleep
RegSysMisc
h0013
r0
RegSysWd
h0014
r0
RegSysPre0
h0015
r0
RegSysRcTrim1
h001B
r0
RegSysRcTrim2
h001C
r0
6
EnResetPConf
rw,0,cold
SleepFlag
rc,0,cold
r0
r0
r0
r0
r0
r0
5
EnBusError
rw,0,cold
ResetBusError
rc, 0, cold
EnExtClock
rw,0,cold
r0
r0
r0
r0
4
EnResetWD
rw,0,cold
ResetWD
rc, 0, cold
BiasRC
rw,1,cold
r0
r0
r0
RcFreqRange
rw,0,cold
3
2
1
r0
ResetfromportA
rc, 0, cold
ColdXtal
r,1,sleep
r0
r0
r0
r0
r0
EnableXtal
r0
rw,0,sleep
Output16k
r0
rw,0,sleep
WatchDog[3:0]
s,0000,glob
r0
r0
r0
RcFreqCoarse[3:0]
rw,0001,cold
RcFreqFine[5:0]
rw,00000,cold
0
r0
r0
EnableRC
rw,1,sleep
OutputCpuCk
rw,0,sleep
ClearLowPresca
l
c1r0,0,-
Table 4-4-4. Reset block and clock block registers
© Semtech 2006
www.semtech.com
4-4