Z86L99X 查看數據表（PDF） - Zilog

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Z86L99X

Low-Voltage Microcontrollers with ADC

Zilog 

Z86D990/Z86D991 OTP and Z86L99X ROM

Low-Voltage Microcontrollers with ADC

35

Counter/timer 1 is driven by a timer clock generated by dividing the internal clock

by four. The divide-by-four stage, the 6-bit prescaler, and the 8-bit counter/timer

form a synchronous 16-bit divide chain. Counter/timer T1 can also be driven by an

external input (TIN) using Port P52. Port P56 can serve as a timer output (TOUT)

through which T1 or the internal clock can be output. The timer output toggles at

the end-of-count. Figure 18 is a block diagram of the counter/timer.

OSC

+2

Internal

Clock

External Clock

Clock

Logic

+4

+2

TOUT

P56

6-Bit

Down Counter

8-Bit

Down Counter

IRQ5

Internal Clock

Gated Clock

Triggered Clock

PRE1

Initial Value

Register

T1

Initial Value

Register

T1

Current Value

Register

TINP31

Write

Write

Read

Internal Data Bus

Figure 18. T1 Counter/Timer Block Diagram

PS003807-1002

PRELIMINARY

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