Z8913820ASC 查看數據表（PDF） - Zilog

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Z8913820ASC

VOICE PROCESSING CONTROLLERS

Zilog 

Zilog

Z89138/Z89139

Voice Processing Controllers

Counter/Timers. There are two 8-bit programmable The counters can be programmed to start, stop, restart to

counter/timers (T1,T0), each driven by its own 6-bit pro- continue, or restart from the initial value. The counters can

grammable prescaler. The T1 prescaler is driven by inter-

nal or external clock sources. However, the T0 prescaler is

also be programmed to stop upon reaching zero (single

pass mode) or to automatically reload the initial value and

1

driven by the internal clock only (Figure 24).

continue counting (modulo-n continuous mode).

The 6-bit prescalers can divide the input frequency of the

clock source by any integer number from 1 to 64. Each

prescaler drives its counter, which decrements the value

(0 to 256) that has been loaded into the counter. When the

counter reaches the end of the count, a timer interrupt re-

quest, IRQ4 (T0) or IRQ5 (T1), is generated.

The counters, but not the prescalers, are read at any time

without disturbing their value or count mode. The clock

source for T1 is user-definable and is either the internal mi-

croprocessor clock divided by four, or an external signal in-

put via Port 31. The Timer Mode register configures the ex-

ternal timer input (P31) as an external clock, a trigger input

that can be retriggerable or non-retriggerable, or as a gate

input for the internal clock. The counter/timers can be cas-

caded by connecting the T0 output to the input of T1.

DSP Clock

÷2

D7, D6

(F) OC

(DSP CON)

÷2

D0,D1

(SMR)

÷ 16

÷2

OSC

T0, T2, T3

Internal Data Bus

Write

Write

Read

PRE0

Initial Value

Register

T0

Initial Value

Register

T0

Current Value

Register

÷4

Internal

Clock

6-Bit

Down

Counter

8-bit

Down

Counter

IRQ4

External Clock

Clock

Logic

÷4

Internal Clock

Gated Clock

Triggered Clock

TIN P31

6-Bit

Down

Counter

÷2

8-Bit

Down

Counter

TOUT

P36

IRQ5

PRE1

Initial Value

Register

T1

Initial Value

Register

T1

Current Value

Register

Write

Write

Read

Internal Data Bus

Figure 24. Counter/Timer Block Diagram

DS97TAD0201

PRELIMINARY

35

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