Z8913820FSC 查看數據表（PDF） - Zilog
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Z8913820FSC Datasheet PDF : 66 Pages
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Z89138/Z89139
Voice Processing Controllers
Z8 FUNCTIONAL DESCRIPTION (Continued)
SCLK/TCLK divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The pur-
pose of this control is to selectively reduce device power
consumption during normal processor execution (SCLK
control) and/or HALT Mode (where TCLK sources
counter/timers and interrupt logic).
Zilog
Stop-Mode Recovery Source (D4-D2). These three bits
of the SMR specify the wake-up source of the Stop-Mode
Recovery (Figure 27 and Table 8).
SMR D4 D3 D2
000
VDD
P31
P32
SMR D4 D3 D2 SMR D4 D3 D2
01 0
10 0
01 1
SMR D4 D3 D2
10 1
P20
P33
HSEC
P23
Stop Mode Recovery Edge
Select (SMR)
P33 From Pads
SMR D4 D3 D2
11 0
P20
P27
SMR D4 D3 D2
11 1
To POR
RESET
To P33 Data
Latch and IRQ1
MUX
Digital/Analog Mode
Select (P3M)
Figure 27. Stop-Mode Recovery Source
Table 8. Stop-Mode Recovery Source
SMR:432
D4 D3 D2
Operation
Description of Action
0
0
0 POR and/or external reset recovery
0
0
1 No effect
0
1
0 P31 transition
0
1
1 P32 transition
1
0
0 P33 transition
1
0
1 HSEC
1
1
0 Logical NOR of P20 through P23
1
1
1 Logical NOR of P20 through P27
Stop-Mode Recovery Delay Select (D5). When Low, this
bit disables the 5 ms /RESET delay after Stop-Mode Re-
covery. The default configuration of this bit is 1. If the “fast”
wake up is selected, the Stop-Mode Recovery source is
kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select (D6). A 1 in this bit po-
sition indicates that a high level on any one of the recovery
sources wakes the Z89138/139 from STOP Mode. A 0 in-
dicates low level recovery. The default is 0 on POR (Table
8).
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP Mode. It is active High, and is 0 (cold)
on POR/WDT /RESET. This bit is Read-Only. It is used to
distinguish between a cold or warm start.
38
PRELIMINARY
DS97TAD0201
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