Z89139 查看數據表（PDF） - Zilog

零件编号

产品描述 (功能)

生产厂家

Z89139

VOICE PROCESSING CONTROLLERS

Zilog 

Z89138/Z89139

Voice Processing Controllers

Z8 FUNCTIONAL DESCRIPTION (Continued)

Watch-Dog Timer Mode Register (WDTMR). The WDT

is a retriggerable one-shot timer that resets the Z8 if it

reaches its terminal count. The WDT is initially enabled by

executing the WDT instruction and refreshed on subse-

quent executions of the WDT instruction. The WDT circuit

Zilog

is driven by an on-board RC oscillator or external oscillator

from the XTAL1 pin. The POR clock source is selected

with bit 4 of the WDT register (Figure 28). The WDTMR

register is accessible only within 64 Z8 clock cycles after

POR.

WDTMR (F) 0F

D7 D6 D5 D4 D3 D2 D1 D0

* Default setting after RESET

WDT TAP

00

01*

10

11

INT RC OSC

5 ms

15 ms

25 ms

100 ms

EXTERNAL CLOCK

256 Tpc

512 Tpc

1024 Tpc

4096 Tpc

WDT During HALT

0 OFF

1 ON*

WDT During STOP

0 OFF

1 ON*

XTAL1/INT RC Select for WDT

0 On-Board RC

1 XTAL

W No effect

R Always "1"

Figure 28. Watch-Dog Timer Mode Register

Half-Second Timer Status Register (HSEC). The half-

second timer status register (Figure 29) is a free-running

timer clocked by the external 32.768 kHz crystal. In normal

operation mode, every half-second, the timer will time-out

and set bit 0 (D0) of the HSEC register to 1. The user can

reset this bit for real timing. In Stop mode, this timer can be

used as a Stop-Mode Recovery source. Every half-sec-

ond, the timer will recover the Stop mode and bit 0 of the

HSEC register will be set to 1. Therefore, in STOP Mode,

the user can keep real time.

HSEC (F) 0E

D7 D6 D5 D4 D3 D2 D1 D0

R 1 Half second time-out

0 No time-out

W 1 No effect

0 RESET the half second timer bit

Reserved R "0"

W No effect

Figure 29. Half-Second Timer Status Register

40

PRELIMINARY

DS97TAD0201

Share Link: