Z8913829ASC 查看數據表（PDF） - Zilog
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Z8913829ASC Datasheet PDF : 66 Pages
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Zilog
Z89138/Z89139
Voice Processing Controllers
ANALOG CONTROL REGISTER (ACR)
The Analog Control register is mapped to register EXT6 of The 16-bit field of EXT6 defines modes of both the A/D and
1 the DSP (Table 17). This read/write register is accessible the D/A. The High Byte configures the D/A while the Low
by the DSP only.
Byte controls the A/D mode.
Table 17. EXT6 Analog Control Register (ACR)
Field
Position
Attrib
MPX_DSP_INT0 f--------------- R/W
Value
1
0
Label
P26
Timer3
20.48
MHz
29.49
MHz*
Reserved
-edcba----------
R
W
Return “0”
No effect
Reserved
------9---------
R
W
Return “1”
No effect
D/A_SamplingRate-------8-------- R/W
DSP_port (DSP1, --------76------ R/W
DSP0)
0
16 kHz
8.04 kHz
1
10 kHz
9.6 kHz
User-defined DSP
outputs
Enable A/D
----------5----- R/W
1
A/D Enabled
0
A/D Disabled
ConversionDone -----------4----
W
R
No effect
1
Done
0
Not Done
StartConversion ------------3--- R/W
1
Start
0
Wait Timer
Reserved
-------------2--
R
W
Return “0”
No effect
20/29 MHz Select --------------1- R/W
1
29.49 MHz*
0
20.48 MHz†
A/D_SamplingRate---------------0 R/W
1
0
Notes:
* Default value
† Optional feature
16 kHz
8 kHz
16 kHz
9.6 kHz
DS97TAD0201
PRELIMINARY
49
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