Z8913929ASC 查看數據表（PDF） - Zilog

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Z8913929ASC

VOICE PROCESSING CONTROLLERS

Zilog 

Zilog

Z89138/Z89139

Voice Processing Controllers

Pulse Width Modulator (PWM)

slot of each of the 32 groups represents Low_Val, while

The PWM supports two different sampling rates (10 and 16

kHz), according to the settings of bit 8 of the ACR. The out-

put of the PWM can be assigned to logic 1 only during the

High_Val is represented by the remaining 31 time slots in

each group.

For example, a value of %13a is loaded into PWM data

1

active region (which is 4/5 of the output signal period). The register EXT 5:

output will be at logic 0 for the rest of the time. An excep-

tion occurs in 10 kHz PWM, where the active region covers

%13a = 01 0011 1010B = 314

the whole output signal period (Figure 39). The active re-

gion is divided into 1024 time slots. In each of these time

High_Val = 01001B = 9

slots, the output can be set to logic 1 or logic 0.

Low_Val = 11010B = 26

In order to increase the effective sampling rate, the PWM

employs a special technique of distributing the “logic 1” pe- 26 out of 32 groups will then have their first slots set to log-

riod over the active region.

ic 1. The remaining one slot in each group has nine time

slots set to logic 1.

The 10-bit PWM data is divided into two parts: the upper

five bits (High_Val) and the lower five bits (Low_Val). The For 10 kHz PWM, the effective output frequency is 10K x

1024 time slots in the active region are divided into 32 32 = 320 kHz. Figure 40 illustrates the waveform by using

equal groups, with 32 time slots in each group. The first a 6-bit PWM data (3-bit High_Val and 3-bit Low_Val).

100 µs

250 µs

10 kHz

16 kHz

Figure 38. PWM Waveform (shaded area shows the active region)

DS97TAD0201

PRELIMINARY

51

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