Z89C0015VSC 查看數據表（PDF） - Zilog

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Z89C0015VSC

16-BIT DIGITAL SIGNAL PROCESSOR

Zilog 

ZILOG

CLK

/EI

ER//W

EXT15-EXT0

EA2-EA0

/RDYE

PRELIMINARY

1

2

8

5

11

Z89C00

16-BIT DIGITAL SIGNAL PROCESSOR

9

10

5

EXT Bus: Input

Valid Data In

Valid Address Out

19

20

Figure 18. Read From External Device Timing

(/RDYE used to hold data one clock cycle)*

Note: * /RDYE is checked during rising edge of clock.

DC 4083-00

25

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