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DSM2190F4

DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-2191 DSPs (3.3V Supply)

STMicroelectronics 

DSM2190F4

SUMMARY DESCRIPTION

The DSM2190F4 is a system memory device for

use with the Analog Devices ADSP-2191 DSP.

DSM means Digital signal processor System

Memory. A DSM device brings In-System Pro-

grammable (ISP) Flash memory, parameter stor-

age, programmable logic, and additional I/O to

DSP systems. The result is a simple and flexible

two-chip solution for DSP designs. DSM devices

provide the flexibility of Flash memory and smart

JTAG programming techniques for both manufac-

turing and the field. On-chip integrated memory

decode logic makes it easy to map dual banks of

Flash memory to the ADSP-2191 in a variety of

ways for bootloading, code execution, data re-

cording, code swapping, and parameter storage.

JTAG ISP reduces development time, simplifies

manufacturing flow, and lowers the cost of field up-

grades. The JTAG ISP interface eliminates the

need for sockets and pre-programmed memory

and logic devices. For manufacturing, end prod-

ucts may be assembled with a blank DSM device

soldered to the circuit board and programmed at

the end of the manufacturing line in 10 to 25 sec-

onds with no involvement of the DSP. This allows

efficient means to test product and manage inven-

tory by rapidly programming test code, then appli-

cation code as determined by inventory

requirements (Just-In Time inventory). Additional-

ly, JTAG ISP reduces development time by turning

fast iterations of DSP code in the lab. Code up-

dates in the field require no disassembly of prod-

uct. The FlashLINKTM JTAG programming cable

costs $59 USD and plugs into any PC or note-

book parallel port.

In addition to ISP Flash memory, DSM devices

add programmable logic (PLD) and up to 16 con-

figurable I/O pins to the DSP system. The state of

each I/O pin can be driven by DSP software or

PLD logic. PLD and I/O configuration are program-

mable by JTAG ISP, just like the Flash memory.

The PLD consists of more than 3000 gates and

has 16 macro cell registers. Common uses for the

PLD include chip selects for external devices,

state-machines, simple shifters and counters, key-

pad and control panel interfaces, clock dividers,

handshake delay, multiplexers, etc. This elimi-

nates the need for small external PLDs and logic

devices. Configuration of PLD, I/O, and Flash

memory mapping are easily entered in a point-

and-click environment using the software develop-

ment tool, PSDsoft ExpressTM. This software is

available at no charge from www.st.com/psm.

Figure 2. System Block Diagram, Two-Chip Solution

16 FLAGS

TIMER/

CAPTURE

SERIAL

DEVICE

SERIAL

DEVICE

SERIAL

DEVICE

UART

DEVICE

HOST

MCU

DSM2190F4

DSP SYSTEM MEMORY

ANALOG

DEVICES

DSP

ADSP-2191

22 ADDRESS

WR, RD, BMS, MSx, IOMS

8 DATA

PRIMARY

FLASH MEMORY

256K X 8

SECONDARY

FLASH MEMORY

32K X 8

16 MACROCELL PLD

I/O CONTROL

POWER MANAGEMENT

CONTENT SECURITY

8 I/O

PORTS

I/O, PLD, CHIP SELECTS

8 I/O

PORTS

I/O, PLD, CHIP SEL

JTAG

ISP TO

ALL

AREAS

JTAG ISP

JTAG DEBUG

AI04959B

4/61

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