PIC16C55X
FIGURE 6-9:
TIMEOUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): CASE 3
VDD
MCLR
INTERNAL POR
PWRT TIMEOUT
TPWRT
OST TIMEOUT
INTERNAL RESET
FIGURE 6-10:
VDD
VDD
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
D
R
R1
MCLR
C
PIC16C55X
TOST
Note 1: External Power-on Reset circuit is required only if
VDD power-up slope is too slow. The diode D helps
discharge the capacitor quickly when VDD powers
down.
2: < 40 k is recommended to make sure that voltage
drop across R does not violate the device’s electrical
specification.
3: R1 = 100 to 1 k will limit any current flowing into
MCLR from external capacitor C in the event of
MCLR/VPP pin breakdown due to Electrostatic Dis-
charge (ESD) or Electrical Overstress (EOS).
DS40143E-page 40
Preliminary
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