C8051F330-GP 查看數據表（PDF） - Silicon Laboratories

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C8051F330-GP

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F330/1/2/3/4/5

SCK*

MISO

T

MCKH

T

MCKL

T

MIS

T

MIH

MOSI

* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.

Figure 17.8. SPI Master Timing (CKPHA = 0)

SCK*

MISO

T

MCKH

T

MCKL

T

MIS

T

MIH

MOSI

* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.

Figure 17.9. SPI Master Timing (CKPHA = 1)

Rev. 1.5

175

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