CS48500 查看數據表（PDF） - Cirrus Logic

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CS48500

32-bit Audio Decoder DSP Family

Cirrus Logic 

5.14 Switching Characteristics — DSD Slave Input Port

CS48500 Data Sheet

32-bit Audio Decoder DSP Family

Parameter

Symbol

Min

Typ Max Unit

MCLK Duty Cycle

-

40

-

60

%

DSD_SCLK Pulse Width Low

DSD_SCLK Pulse Width High

DSD_SCLK Frequency

(64x Oversampled)

tsclkl

tsclkh

-

78

78

1.024

-

-

ns

-

-

ns

-

3.2

MHz

(128x Oversampled) -

2.048

-

6.4

MHz

DSD_A / _B valid to DSD_SCLK rising setup time

tsdlrs

20

-

-

ns

DSD_SCLK rising to DSD_A or DSD_B hold time

DSD clock to data transition (Phase Modulation mode)

tsdh

tdpm

20

-

-

ns

DRAFT -20

-

20

ns

IAL HI Figure 8. Direct Stream Digital - Serial Audio Input Timing

IDENTDELP DSD_SCLK

(128Fs)

DSD_SCLK

F(64Fs)

CONDSD_A, DSD_B

t dpm

t dpm

Figure 9. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode

DS734A3

©Copyright 2006 Cirrus Logic, Inc.

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