PSD4252F6-70UT 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

PSD4252F6-70UT

Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

STMicroelectronics 

PSD4235G2

Memory ID Registers

The 8-bit read-only Memory Status Registers are

included in the CSIOP space. The user can deter-

mine the memory configuration of the PSD device

by reading the Memory ID0 and Memory ID1 reg-

isters. The content of the registers is defined as

shown in Table 26 and Table 27.

PLDs

The PLDs bring programmable logic functionality

to the PSD. After specifying the logic for the PLDs

using PSDsoft Express, the logic is programmed

into the device and available upon Power-up.

Table 32. DPLD and CPLD Inputs

Input Source

Input Name

Number

of

Signals

MCU Address Bus1 A15-A0

16

MCU Control Signals CNTL0-CNTL2

3

Reset

RST

1

Power-down

PDN

1

Port A Input

Macrocells

PA7-PA0

8

Port B Input

Macrocells

PB7-PB0

8

Port C Input

Macrocells

PC7-PC0

8

Port D Inputs

PD3-PD0

4

Port F Inputs

PF7-PF0

8

Page Register

PGR7-PGR0

8

Macrocell A Feedback MCELLA.FB7-FB0

8

Macrocell B Feedback MCELLB.FB7-FB0

8

Flash memory

Program Status Bit

Ready/Busy

1

Note: 1. The address inputs are A19-A4 in 80C51XA mode.

The PSD contains two PLDs: the Decode PLD

(DPLD), and the Complex PLD (CPLD). The PLDs

are briefly discussed in the next few paragraphs,

and in more detail in the following sections. Figure

12 shows the configuration of the PLDs.

The DPLD performs address decoding for internal

components, such as memory, registers, and I/O

ports Select signals.

The CPLD can be used for logic functions, such as

loadable counters and shift registers, state ma-

chines, and encoding and decoding logic. These

logic functions can be constructed using the 16

Output Macrocells (OMC), 24 Input Macrocells

(IMC), and the AND Array. The CPLD can also be

used to generate External Chip Select (ECS0-

ECS2) signals.

The AND Array is used to form product terms.

These product terms are specified using PSDsoft

Express. An Input Bus consisting of 82 signals is

connected to the PLDs. The signals are shown in

Table 32.

The Turbo Bit in PSD. The PLDs in the

PSD4235G2 can minimize power consumption by

switching to standby when inputs remain un-

changed for an extended time of about 70 ns. Re-

setting the Turbo bit to 0 (Bit 3 of the PMMR0

register) automatically places the PLDs into stand-

by if no inputs are changing. Turning the Turbo

mode off increases propagation delays while re-

ducing power consumption. See the section enti-

tled “Power Management”, on page 59, on how to

set the Turbo bit.

Additionally, five bits are available in the PMMR2

register to block MCU control signals from entering

the PLDs. This reduces power consumption and

can be used only when these MCU control signals

are not used in PLD logic equations.

Each of the two PLDs has unique characteristics

suited for its applications. They are described in

the following sections.

31/89

Share Link: