PSD4203G3V-15UT 查看數據表（PDF） - STMicroelectronics
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PSD4203G3V-15UT
STMicroelectronics
PSD4203G3V-15UT Datasheet PDF : 89 Pages
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PSD4235G2
Figure 25. Interfacing the PSD with an MMC2001
VCC_BAR
VCC_BAR
A[19:16]
AD[15:0]
U3
CRYSTAL
Infineon C167CR
100
138
AD0 101
XTAL1
AD1 102
AD2 103
AD3 104
137
AD4 105
XTAL2
AD5 106
65
AD6 107
66 P3.0/T0IN
AD7
67 P3.1/T6OUT
108
68 P3.2/CAPIN
AD8 111
69 P3.3/T3OUT
AD9 112
70 P3.4/T3EUD
AD10 113
73 P3.5/T4IN
AD11 114
74 P3.6/T3IN
AD12 115
75 P3.7/T2IN
AD13 116
76 P3.8/MRST
AD14 117
77 P3.9/MTSR
AD15
78 P3.10/TXD0
P3.11/RXD0
80
81 P3.13/SCLK
P3.15/CLKOUT
85
P4.0/A16 86
A17 87
A18 88
A19 89
A16
A17
A18
A19
27
A20 90
28 P5.0/AN0
A21 91
29 P5.1/AN1
A22 92
30
31
P5.2/AN2
P5.3/AN3
P4.7/A23
WR/WRL
96
95
32 P5.4/AN4
RD 79
33 P5.5/AN5
P3.12/BHE/WRH 98
34 P5.6/AN6
ALE
35 P5.7/AN7
99
36 P5.8/AN8
EA
39
40
P5.9/AN9
P5.10/AN10/T6UED
P1H7
135
134
41
42
P5.11/AN11/T5UED
P5.12/AN12/T6IN
P1H6
P1H5
133
132
43 P5.13/AN13/T5IN
P1H4 131
44
P5.14/AN14/T4UED
P5.15/AN15/T2UED
P1H3
P1H2
130
129
1
2
P6.0/!CS0
P1H1
P1H0
128
125
3
4
P6.1/!CS1
P6.2/!CS2
P1L7
P1L6
124
123
5 P6.3/!CS3
P1L5 122
6
7
P6.4/!CS4
P6.5/!HOLD
P1L4
P1L3
121
120
8
P6.6/!HLDA
P6.7/!BREQ
P1L2
P1L1
119
118
19
20
21
P7.0/POUT0
P7.1/POUT1
P1L0
P2.0/CC0IO
47
48
22
23
P7.2/POUT2
P7.3/POUT3
P2.1/CC1IO
P2.2/CC2IO
49
50
24
25
P7.4/CC28IO
P7.5/CC29IO
P2.3/CC3IO
P2.4/CC4IO
51
52
26
P7.6/CC30IO
P7.7/CC31IO
9
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
53
54
57
10
11
P8.0/CC16IO
P8.1/CC17IO
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
58
59
12
13
14
15
16
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P2.10/CC10IO/EX2IN
P2.11/CC11IO/EX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
60
61
62
63
64
P8.7/CC23IO
P2.15/CC15IO/EX7IN
37
97
Vref
READY
140
RSTIN
RSTOUT
NMI
141
142
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
PSD
3
4 ADIO0
5 ADIO1
6 ADIO2
7 ADIO3
10 ADIO4
11 ADIO5
12 ADIO6
ADIO7
13
14 ADIO8
15 ADIO9
16 ADIO10
17 ADIO11
18 ADIO12
19 ADIO13
20 ADIO14
ADIO15
WR\
RD\
BHE\
ALE
RESET\
59
60 CNTL0(WR)
CNTL1(RD)
40
CNTL2(BHE)
79
80 PD0 (ALE)
1 PD1 (CLKIN)
2 PD2 (CSI)
PD3 (WRH)
39
RESET
71
72 PE0 (TMS)
73
74
PE1 (TCK/ST)
PE2 (TDI)
75
76
PE3 (TDO)
PE4 (TSTAT/RDY)
77
78
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
31
PF0 32
PF1 33
PF2 34
PF3 35
PF4 36
PF5 37
PF6 38
PF7
21
PG0 22
PG1 23
PG2 24
PG3 25
PG4 26
PG5 27
PG6 28
PG7
51
PA0 52
PA1 53
PA2 54
PA3 55
PA4 56
PA5 57
PA6 58
PA7
61
PB0 62
PB1 63
PB2 64
PB3 65
PB4 66
PB5
PB6
67
68
PB7
41
PC0 42
PC1
PC2
43
44
PC3
PC4
45
46
A16
A17
A18
A19
PC5
PC6
47
48
PC7
A[19:16]
ADIO[15:0]
RESET\
MMC2001. The Motorola MCORE MMC2001
MCU has a MOD input pin that selects interal or
external boot ROM. The PSD can be configured
as the external flash boot ROM or as extension to
the internal ROM.
The MMC2001 has a 16-bit external data bus and
20 address lines with external chip select signals.
The Chip Select Control Registers allow the user
to customize the bus interface and timing to fit the
individual system requirement. A typical interface
AI04954b
configuaration to the PSD is shown in Figure 25.
The MMC2001’s R/W signal is conneced to the
CNTL0 pin, while EB0 and EB1 (enable byte-0 and
enable byte-1) are connected to the CNTL1 (UDS)
and CNTL2 (LDS) pins. The WEN bit in the Chip
Select Control Register should be set to 1 to termi-
nate the EB0-EB1 earlier to provide the wrtie data
hold time for the PSD. The WSC and WWS bits in
the Control Register are set to wait states that
meet the PSD access time requirement.
47/89
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