FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
SCK Cycle #
(for reference)
SCK (CPOL=0)
1
2
3
4
5
6
7
8
SCK (CPOL=1)
MOSI
(from Master)
MISO
(from Slave)
SS# (to Slave)
MSB
6
5
4
3
2
1
LSB
MSB
6
5
4
3
2
1
LSB
*
* Not defined, but normally MSB of next received byte
555 ILL F16.0
FIGURE 6-2: SPI TRANSFER FORMAT WITH CPHA = 0
SCK Cycle #
(for reference)
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(from Master)
MISO
(from Slave)
SS# (to Slave)
1
2
3
4
5
6
7
MSB 6
5
4
3
2
1
* MSB 6
5
4
3
2
1
* Not defined but normally LSB of previously transmitted character
8
LSB
LSB
555 ILL F17.0
FIGURE 6-3: SPI TRANSFER FORMAT WITH CPHA = 1
©2001 Silicon Storage Technology, Inc.
41
S71207-00-000 9/01 555