ML6430 查看數據表（PDF） - Micro Linear Corporation

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产品描述 (功能)

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ML6430

Genlocking Sync Generator with Digital Audio Clock for NTSC, PAL & VGA

Micro Linear Corporation 

ML6430/ML6431

REGISTER DATA

BIT

7

0 Test 3

7

1 Test 1

7

2 Ext 54

Clock IN

7

3 Test 4

8

0 FAud0

8

1 FAud1

8

2 VCR

8

3 SLEEP

9

0 Thresh0

9

1 Thresh1

9

2 VGA

9

3 Div4

10

0 FStd0

10

1 FStd1

10

2 FStd2

10

3

PALXTAL

DESCRIPTION

VALUE RANGE

For test mode only:

No user programmable features Set to 0

For test mode only:

No user programmable features Set to 0

Low = Pin 3 is SLEEP

High = Pin 3 is 54MHz Clock

For test mode only:

No user programmable features Set to 0

AudioClk Freq Bit 0

00 = 48kHz, 01 = 44.1kHz, 10 = 32kHz

AudioClk Freq Bit 1

Enable VCR Mode

High = Enabled, Low = Disabled

Power Down Mode

High = Power Down, Low = Normal

Select ‘Out of Lock’ Threshold 00 = 2.5 Pixels 10 = 1.0 Pixels

01 = 2.5 Pixels 11 = 4.0 Pixels

Enable VGA Mode

High = Enabled, Low = Disabled

Enable /4 on M/N Loop

High = Enabled, Low = Disabled

Freq Std Sel Bit 0

000 = NTSC Sq Pix 011 = PAL 601

Freq Std Sel Bit 1

001 = PAL Sq Pix 100 = NTSC 4Fsc

Freq Std Sel Bit 2

010 = NTSC 601 101 = PAL 4Fsc

Enable PAL Ref Freq

High = Enabled, Low = Disabled

BIT CODE

RANGE

0

0

0 or 1

0

00 to 10

0 or 1

00 to 11

0 or 1

0 or 1

000 to 101

0 or 1

Table 10. ML6430 Register Map (Continued)

19

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