ML6430 查看數據表（PDF） - Micro Linear Corporation

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ML6430

Genlocking Sync Generator with Digital Audio Clock for NTSC, PAL & VGA

Micro Linear Corporation 

SERIAL BUS LOGIC (Continued)

PARAMETER

CONDITIONS

SYSTEM TIMING (Continued)

Wait Time From STOP to START

On SDATA (tWAIT)

Hold Time for START On SDATA (tHD/START)

Setup Time for START On SDATA (tSU/START)

Min LOW Time On SCLK (tLOW)

Min HIGH Time On SCLK (tHI)

Hold Time On SDATA (tHD/DATA)

Setup Time On (tSU/DATA)

Fast mode (Note 2)

Slow mode (Note 2)

Rise Time for SCLK & SDATA (tLH)

Fall Time for SCLK & SDATA (tHL)

Setup Time for STOP On SDATA (tSU/STOP)

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

Note 2: Parameter is Luma dependent.

Note 3: Reclock time after bounce.

Note 4: Net phase error for single isolated missing H pulse.

Note 5: Net phase error for glitch at sync level <50ns.

MIN

1.3

0.6

100

250

ML6430/ML6431

TYP

MAX

UNITS

1.3

µs

0.6

µs

0.6

µs

µs

µs

5.0

µs

ns

ns

30

300

ns

30

300

ns

0.6

µs

COMPOSITE

VIDEO IN

PIN 6

REGENERATED

CSYNC

PIN 26

EQUALIZERS

SERRATIONS

HBLANK

PIN 25

SCLAMP

PIN 28

BGATE

PIN 27

BCLAMP

PIN 27

HRESET

PIN 23

tHSW

tHEQW

tHSERRW

tHBLK

tHBLKW

tHSTC

tHSTCW

tHBPC

tHBPGW

tHRW

tHBPCW

Figure 1. Line Rate Waveforms

NOTE: NOT TO SCALE

7

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