PIC16F636T-I/SL(2005) 查看數據表（PDF） - Microchip Technology

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PIC16F636T-I/SL
(Rev.:2005)

8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC12F635/PIC16F636/639

15.11 AC Characteristics: Analog Front-End for PIC16F639 (industrial, extended) (Continued)

AC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Supply Voltage

2.0V ≤ VDD ≤ 3.6V

Operating temperature

-40°C ≤ TAMB ≤ +85°C for industrial

-40°C ≤ TAMB ≤ +125°C for extended

LC Signal Input

Sinusoidal 300 mVPP

Carrier Frequency

125 kHz

LCCOM connected to VSS

Param

No.

Sym.

CTUNZ

Characteristic

LCZ Tuning Capacitor

Min

Typ†

Max

Units

Conditions

VDD = 3.0V,

—

0

—

pF Config. Reg. 3, bits<6:1> Setting = 000000

44.1

63

81.9

pF 63 pF +/- 30%

Config. Reg. 3, bits<6:1> Setting = 111111

63 steps, 1 pF/step

Monotonic increment in capacitor value from

setting = 000000 to 111111 by design

C_Q Q of Trimming Capacitors

50*

—

—

pF Characterized at bench test

TDR Demodulator Charge Time

—

50

—

(delay time of demodulated output

to rise)

μs VDD = 3.0V

MOD depth setting = 50%

Input conditions:

Amplitude = 300 mVPP

Modulation depth = 80%

TDF Demodulator Discharge Time

—

50

—

(delay time of demodulated output

to fall)

μs VDD = 3.0V

MOD depth setting = 50%

Input conditions:

Amplitude = 300 mVPP

Modulation depth = 80%

TLFDATAR Rise time of LFDATA

—

0.5

—

μs VDD = 3.0V

Time is measured from 10% to 90% of

amplitude

TLFDATAF Fall time of LFDATA

—

0.5

—

μs VDD = 3.0V

Time is measured from 10% to 90% of

amplitude

TAGC AGC stabilization time

—

3.5*

—

ms Time required for AGC stabilization

TPAGC High time after AGC settling time

—

62.5

—

μs Equivalent to two Internal clock cycle (FOSC)

TSTAB

AGC stabilization time plus high

time (after AGC settling time)

(TAGC + TPAGC)

4

—

—

ms AGC stabilization time

TGAP Gap time after AGC settling time

200

—

—

μs Typically 1 TE

TRDY Time from exiting Sleep or POR to

—

—

50*

ms

being ready to receive signal

TPRES Minimum time AGC level must be

5*

—

—

ms AGC level must not change more than 10%

held after receiving AGC Preserve

during TPRES.

command

FOSC Internal RC oscillator frequency

(±10%)

28.8

32

35.2

kHz Internal clock trimmed at 32 kHz during test

TINACT Inactivity timer time-out

14.4

16

17.6

ms 512 cycles of RC oscillator @ FOSC

TALARM Alarm timer time-out

28.8

32

35.2

ms 1024 cycles of RC oscillator @ FOSC

RLC LC Pin Input Impedance

LCX, LCY, LCZ

—

1*

—

MOhm Device in Standby mode

*

†

Note 1:

2:

Parameter is characterized but not tested.

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Required output enable filter high time must account for input path analog delays = TOEH - TDR + TDF

Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF)

© 2005 Microchip Technology Inc.

Preliminary

DS41232B-page 169

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