IMSA110 查看數據表（PDF） - STMicroelectronics

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IMSA110

IMAGE AND SIGNAL PROCESSING SUB–SYSTEM

STMicroelectronics 

IMSA110

Figure 6

1

2

3

CLK

PSRIN

PSROUT

PSRIN latched

PIN DESIGNATIONS

System services

Pin

VCC, GND

CLK

RESET

In/out

in

in

Function

Power supply and return

Input clock

System reset

Synchronous input/output

Pin

PSRin[7-0]

PSRout[7-0]

Cin[21-0]

Cout[21-0]

In/out

in

out

in

out

Function

Programmable shift register

input

Programmable shift register

output

Cascade input port

Cascade output port

Asynchronous input/output

Pin

In/out

Function

E1, E2

W

ADR[8-0]

in

Memory interface enable

signals

in

Memory interface write

enable

in Memory interface adress bus

D[7-0]

in/out Memory interface data bus

Note : Signal names are shown with an overbar if they are active

low, otherwise they are active high.

8.1 System services

System services include all the necessary logic to

start up and maintain the IMS A110.

Power

Power is supplied to the device via the VCC and

GND pins. Several of each are provided to mini-

12/26

mise inductance within the package. All supply pins

must be connected. The supply must be decoupled

close to the chip by at least one 100nF low induc-

tance (e.g. ceramic) capacitor between VCC and

GND.

CLK

The clock signal CLK controls the timing of input

and the output on the four dedicated interfaces, and

controls the progress of data through the shift reg-

isters, multiply-accumulate array and post-proc-

essing unit. The A110 is fully static so the clock can

be slowed down or stopped in either state without

corrupting data.

RESET

If this pin is taken low for at least 2 clock cycles, the

control logic within the IMS A110 will be reset and

all of the control and configuration registers will be

initialised to their default values. All other register,

memory locations, datapath registers and shift reg-

isters will not be reset by this signal.

A reset is initiated automatically when power is first

applied to the device. This reset will be completed

once four cycles of CLK have occured after VCC is

valid.

8.2 Synchronous services

PSRin[7-0]

This 8-bit wide bus supplies input data to the de-

vice. The input data enters the first of the three shift

registers in the chain. The timing of this input is

controlled by the CLK signal. The data on the

PSRin port is sampled on the rising edge of the

clock. In a cascade arrangement, this bus will be

connected to the PSRout port of the previous de-

vice. In such an arrangement the PSRin port on the

first device will be the input to the overall cascaded

system.

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