MC9S08SH8CSC 查看數據表（PDF） - Freescale Semiconductor
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MC9S08SH8CSC Datasheet PDF : 341 Pages
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Chapter 10 Internal Clock Source (S08ICSV2)
10.1.4.4 FLL Bypassed Internal Low Power (FBILP)
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock. The BDC clock is not available.
10.1.4.5 FLL Bypassed External (FBE)
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external
clock source. The BDC clock is supplied from the FLL.
10.1.4.6 FLL Bypassed External Low Power (FBELP)
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The external reference clock can be an external crystal/resonator
supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is
not available.
10.1.4.7 Stop (STOP)
In stop mode the FLL is disabled and the internal or external reference clocks can be selected to be enabled
or disabled. The BDC clock is not available and the ICS does not provide an MCU clock source.
10.2 External Signal Description
There are no ICS signals that connect off chip.
10.3 Register Definitio
Figure 10-1 is a summary of ICS registers.
Table 10-1. ICS Register Summary
Name
R
ICSC1
W
R
ICSC2
W
R
ICSTRM
W
R
ICSSC
W
7
6
CLKS
BDIV
0
0
5
4
3
2
RDIV
IREFS
RANGE HGO
LP
EREFS
TRIM
0
IREFST
CLKST
1
0
IRCLKEN IREFSTEN
ERCLKEN EREFSTEN
OSCINIT
FTRIM
MC9S08SH8 MCU Series Data Sheet, Rev. 3
Freescale Semiconductor
153
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