ML6461CS 查看數據表（PDF） - Micro Linear Corporation
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ML6461CS Datasheet PDF : 30 Pages
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ML6461
FUNCTIONAL DESCRIPTION (Continued)
fields (1-2) and (3-4). The ML6461 also supports a frame
based synchronization mode (B17 = FSYNC = 1) where a
vertical reset pulse unconditionally resets the vertical line
counter to line 4. For proper operation only one active
edge should be sent per frame. The polarity is controlled
by SENSE_VSYNC (B10).
HSYNC
VSYNC
HSYNC
Line 3
Line 4
Coincident
Active Edges
Line 5
Line 6
Beginning of
an Odd Field
Line 265
Line 266
Line 267
Line 268
Line 269
VSYNC
Beginning of
an Even Field
Figure 1. Example of the Beginning of the Odd And Even Fields vs. HSYNC and VSYNC in Master Mode.
(SLAVE/MASTER = 0, SENSE_HSYNC = 0, SENSE_VSYNC = 0)
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