ML6460CS 查看數據表（PDF） - Micro Linear Corporation
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ML6460CS Datasheet PDF : 30 Pages
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FUNCTIONAL DESCRIPTION (Continued)
SLAVE/MASTER, B28 This bit determines if device
operates in master or slave modes. Configuration of
HSYNC, VSYNC and FIELD are determined upon
selection of this bit. Table 3 provides a summary of Slave
/ Master modes. When this bit is set (B28=1), the
ML6460 is in slave mode. When this bit is cleared
(B28=0), the ML6460 is in master mode. Special note for
slave modes: this bit (B28) along with the
SLAVE_MODE bit (B26) selects between internal
(B26=1) and external slave modes (B26=0).
SELCCIR, B27 This bit determines the frequency of
choice between CCIR656 clock rate(27MHz) and Square
Pixel clock rate (24.54MHz). When this bit is set
(B27=1), CCIR656 clock rate is selected. When this bit is
cleared (B27=0), the Square Pixel clock rate is selected.
ML6460
SLAVE_MODE, B26 This bit determines the choice of
two slave modes: internal slave mode or external slave
mode. In internal slave mode (B26=1), horizontal and
vertical timing information is embedded in the YCrCb
data (via SAV / EAV codes); while the HSYNC and
VSYNC pins can be used as outputs. In external slave
mode (B26=0), horizontal and vertical sync pulses must
be provided for timing and synchronization;in this case
HSYNC and VSYNC pins are inputs. See Table 3.
HRESET_MODE, B25 This bit determines whether the
HSYNC is given at the beginning of active video (B25=1)
or HSYNC is given at the beginning of blanking (B25=0).
This bit (B25) is only available for external slave modes.
50 ±2 IRE
10.5
±0.25µs
12.91µs
7 CYCLES
3.58MHz
COLOR
BURST
BLANK
LEVEL
40 IRE
TWO: 7 BIT + PARITY BIT
S
T
A A0 ~ A6 A7 A8 ~ A14 A15
R
T
LINE 21
SYNC
LEVEL
10.003
±0.25µs
27.382µs
33.764µs
Closed Caption on Line21
[CC_21 = 1 and CC_284 = 0]
50 ±2 IRE
10.5
±0.25µs
12.91µs
7 CYCLES
3.58MHz
COLOR
BURST
BLANK
LEVEL
40 IRE
TWO: 7 BIT + PARITY BIT
S
T
A A0 ~ A6 A7 A8 ~ A14 A15
R
T
LINE 284
SYNC
LEVEL
10.003
±0.25µs
27.382µs
33.764µs
Closed Caption on Line284
[CC_21 = 0 and CC_284 = 1]
50 ±2 IRE
10.5
±0.25µs
12.91µs
7 CYCLES
3.58MHz
COLOR
BURST
BLANK
LEVEL
40 IRE
TWO: 7 BIT + PARITY BIT
S
T
A A0 ~ A6 A7 A8 ~ A14 A15
R
T
LINE 21
50 ±2 IRE
10.5
±0.25µs
12.91µs
7 CYCLES
3.58MHz
COLOR
BURST
BLANK
LEVEL
40 IRE
TWO: 7 BIT + PARITY BIT
S
T
A A16 ~ A22 A23 A24 ~ A30 A31
R
T
LINE 284
SYNC
LEVEL
10.003
±0.25µs
27.382µs
SYNC
LEVEL
10.003
±0.25µs
33.764µs
27.382µs
Closed Caption on Line21 and Line 284
[CC_21 = 1 and CC_284 = 1]
Figure 13. Closed Caption on Line 21 and Line 284.
33.764µs
19
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