PSD933F3V-20UI 查看數據表（PDF） - STMicroelectronics

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PSD933F3V-20UI

Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

STMicroelectronics 

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

INITIAL DELIVERY STATE

When delivered from ST, the PSD device has all

bits in the memory and PLDs set to ’1.’ The PSD

Configuration Register bits are set to ’0.’ The code,

configuration, and PLD logic are loaded using the

programming procedure. Information for program-

ming the device is available directly from ST.

Please contact your local sales representative.

Table 35. JTAG Enable Register

0 = off JTAG port is disabled.

Bit 0 JTAG_Enable

1 = on JTAG port is enabled.

Bit 1

X

0 Not used, and should be set to zero.

Bit 2

X

0 Not used, and should be set to zero.

Bit 3

X

0 Not used, and should be set to zero.

Bit 4

X

0 Not used, and should be set to zero.

Bit 5

X

0 Not used, and should be set to zero.

Bit 6

X

0 Not used, and should be set to zero.

Bit 7

X

0 Not used, and should be set to zero.

Note: 1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Config-

uration bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is

used to enable the JTAG signals.

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