PSD854F2VA-90UI 查看數據表（PDF） - STMicroelectronics

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PSD854F2VA-90UI

Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V

STMicroelectronics 

Sector Select and SRAM Select

PSD8XXFX

PSDsoft Express Configuration to configure it for Boot-up and having the MCU change it

when desired. Table 14 describes the VM register.

Figure 8. Priority level of memory and I/O components

Highest Priority

Lowest Priority

Level 1

SRAM, I/O, or

Peripheral I/O

Level 2

Secondary

Non-Volatile Memory

Level 3

Primary Flash Memory

AI02867D

12.3

12.3.1

12.3.2

Configuration modes for MCUs with separate program and

data spaces

Separate Space modes

Program space is separated from data space. For example, Program Select Enable (PSEN,

CNTL2) is used to access the program code from the primary Flash memory, while Read

Strobe (RD, CNTL1) is used to access data from the secondary Flash memory, SRAM and

I/O port blocks. This configuration requires the VM register to be set to 0Ch (see Figure 9).

Combined Space modes

The program and data spaces are combined into one memory space that allows the primary

Flash memory, secondary Flash memory, and SRAM to be accessed by either Program

Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to configure the

primary Flash memory in Combined space, Bits b2 and b4 of the VM register are set to '1'

(see Figure 10).

Figure 9. 8031 memory modules – separate space

DPLD

RS0

CSBOOT0-3

FS0-FS7

PSEN

RD

Primary

Flash

Memory

CS

OE

Secondary

Flash

Memory

CS

OE

SRAM

CS

OE

AI02869C

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Doc ID 7833 Rev 7

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