PC48F0000P0ZB00 查看數據表（PDF） - Intel

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PC48F0000P0ZB00

Intel StrataFlash® Embedded Memory

Intel 

1-Gbit P30 Family

Figure 20. Continuous Burst Read, showing an Output Delay Timing

CLK [C]

Address [A]

ADV# [V]

CE# [E]

OE# [G]

WAIT [T]

Data [D/Q]

R301

R302

R306

R2

R101

R105

R106

R303

R102

R3

R304

R304

R304

R15

R4

R7

R307

R304

R312

R305

R305

R305

R305

Notes:

1.

WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to

assert either during or one data cycle before valid data.

2.

At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the

starting address is not 4-word boundary aligned.

April 2005

40

Intel StrataFlash® Embedded Memory (P30)

Order Number: 306666, Revision: 001

Datasheet

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