STM32F21xxx
Application block diagrams
Figure 95. RMII with a 25 MHz crystal and PHY with PLL
MCU
HCLK(1)
STM32F
Ethernet
MAC 10/100
IEEE1588 PTP
Timer
input
TIM2
trigger
Timestamp
comparator
RMII_TX_EN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRX_DV
RMII_REF_CLK
MDIO
MDC
Ethernet
PHY 10/100
RMII
= 7 pins
REF_CLK
RMII + MDC
= 9 pins
XTAL
25 MHz
/2 or /20
2.5 or 25 MHz synchronous 50 MHz
OSC
PLL
HCLK
PLL
MCO1/MC02 PHY_CLK 25 MHz XT1
MS19970V1
1. fHCLK must be greater than 25 MHz.
2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block.
Doc ID 17050 Rev 8
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