Electrical characteristics
5.1.6 Power supply scheme
Figure 16. Power supply scheme
VBAT
1.8-3.6 V
Po wer swi tch
STM32F21xxx
Backup circuitry
(OSC32K,RTC,
Wakeup logic
Backup registers,
backup RAM)
GP I/Os
2 × 2.2 μF VVCCAAPP__12
VDD
15 × 100 nF
+ 1 × 4.7 μF
VDD
1/2/...14/15
VSS
1/2/...14/15
O UT
IN
Voltage
regulator
IO
Logic
Kernel logic
(CPU,
digital
& RAM)
REGOFF
VDD
100 nF
+ 1 μF
VREF
100 nF
+ 1 μF
VDDA
VREF+
VREF-
VSSA
Flash memory
ADC
Analog:
RCs, PLL,
...
MS19041V2
1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be
placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality
of the device.
2. To connect REGOFF pin, refer to Section 2.2.16: Voltage regulator.
3. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is
OFF.
4. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
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Doc ID 17050 Rev 8