M29W800DB70N6 查看數據表（PDF） - STMicroelectronics

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M29W800DB70N6

8-Mbit (1 Mbit x 8 or 512 Kbits x 16, boot block) 3 V supply flash memory

STMicroelectronics 

M29W800DT, M29W800DB

REVISION HISTORY

Table 30. Document Revision History

Date

Version

Revision Details

August 2001

1.0

First Issue

Block Protection Appendix added, SO44 drawing and package mechanical data updated,

03-Dec-2001

2.0

CFI Table 26, address 39h/72h data clarified, Read/Reset operation during Erase

Suspend clarified

Description of Ready/Busy signal clarified (and Figure 15. modified)

01-Mar-2002

3.0

Clarified allowable commands during block erase

Clarified the mode the device returns to in the CFI Read Query command section

11-Apr-2002

4.0

Temperature range 1 added

Document promoted from Preliminary Data to full Data Sheet

31-Mar-2003

Erase Suspend Latency Time (typical and maximum) and Data Retention parameters

added to Table Table 6., Program, Erase Times and Program, Erase Endurance Cycles,

4.1

and Typical after 100k W/E Cycles column removed. Minimum voltage corrected for 70ns

Speed Class in Table 9., Operating and AC Measurement Conditions.

Logic Diagram and Data Toggle Flowchart corrected.

Lead-free package options E and F added to Table 20., Ordering Information Scheme.

TSOP48 package Outline and Mechanical Data updated.

13-Feb-2004

5.0

TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch added.

Table 9.Operating and AC Measurement Conditions updated for 70ns speed option.

23-Apr-2004

6.0

Figure 3., SO Connections updated.

16-Sep-2004

7.0

45ns speed class added.

41/42

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