ST7PLITE39F2U6TR 查看數據表（PDF） - STMicroelectronics

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ST7PLITE39F2U6TR

8-bit MCU with single voltage Flash, data EEPROM, ADC, timers, SPI, LINSCI™

STMicroelectronics 

ST7LITE3xF2

OPTION BYTES (Cont’d)

7

AWU

CK

Default

1

Value

OPTION BYTE 0

0

7

OSCRANGE

2:0

SEC1 SEC0

FMPR

FMPW

PLL

x4x8

PLL

OFF

OPTION BYTE 1

LVD

Res. OSC

1:0

111 1 1

0

0

1

1

10

1

1

0

WDG WDG

SW HALT

11

OPTION BYTE 1

OPT 7 = PLLx4x8 PLL Factor Selection.

0: PLLx4

1: PLLx8

OPT 6 = PLLOFF PLL Disable

This option bit enables or disables the PLL.

0: PLL enabled

1: PLL disabled (bypassed)

OPT 5 = Reserved. Must always be set to 1.

OPT 3:2 = LVD[1:0] Low Voltage Selection

These option bits enable the voltage detection

block (LVD and AVD) with a selected threshold to

the LVD and AVD.

Configuration

VD1 VD0

LVD Off

11

Highest Voltage Threshold

10

Medium Voltage Threshold

01

Lowest Voltage Threshold

00

OPT 4 = OSC RC Oscillator Selection

This option bit enables to select the internal RC

Oscillator.

0: RC Oscillator on

1: RC Oscillator off

Notes:

– RC oscillator available on ST7LITE35 and

ST7LITE39 devices only

– If the RC oscillator is selected, then to improve

clock stability and frequency accuracy, it is rec-

ommended to place a decoupling capacitor, typ-

ically 100nF, between the VDD and VSS pins as

close as possible to the ST7 device.

OPT 1 = WDGSW Hardware or Software Watch-

dog

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

OPT 0 = WDG HALT Watchdog Reset on Halt

0: No reset generation when entering HALT mode

1: Reset generation when entering HALT mode

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