ST7PLITE35F2M6TR 查看數據表（PDF） - STMicroelectronics

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ST7PLITE35F2M6TR

8-bit MCU with single voltage Flash, data EEPROM, ADC, timers, SPI, LINSCI™

STMicroelectronics 

ST7LITE3xF2

SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.4 Clock Phase and Clock Polarity

Four possible timing relationships may be chosen

by software, using the CPOL and CPHA bits (See

Figure 52).

Note: The idle state of SCK must correspond to

the polarity selected in the SPICSR register (by

pulling up SCK if CPOL = 1 or pulling down SCK if

CPOL = 0).

The combination of the CPOL clock polarity and

CPHA (clock phase) bits selects the data capture

clock edge.

Figure 52 shows an SPI transfer with the four com-

binations of the CPHA and CPOL bits. The dia-

gram may be interpreted as a master or slave tim-

ing diagram where the SCK pin, the MISO pin and

the MOSI pin are directly connected between the

master and the slave device.

Note: If CPOL is changed at the communication

byte boundaries, the SPI must be disabled by re-

setting the SPE bit.

Figure 52. Data Clock Timing Diagram

CPHA = 1

SCK

(CPOL = 1)

SCK

(CPOL = 0)

MISO

(from master)

MSBit Bit 6

MOSI

(from slave)

MSBit Bit 6

SS

(to slave)

CAPTURE STROBE

Bit 5 Bit 4

Bit 5 Bit 4

Bit3 Bit 2 Bit 1 LSBit

Bit3 Bit 2 Bit 1 LSBit

SCK

(CPOL = 1)

SCK

(CPOL = 0)

CPHA = 0

MISO

(from master)

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

MOSI

(from slave)

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

SS

(to slave)

CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

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