FBFM2112F897CSLJLS 查看數據表（PDF） - Intel

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FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.0

3.1

3.1.1

Functional Description

This section describes in detail the features and functions supported by

the FM2112.

Ethernet Port Logic (EPL)

The FM2112 contains 24 Ethernet Port Logic transmit and receive pairs;

each pair contains the SerDes, PCS, and a portion of the MAC

functionality.

Port and Lane Configuration

{Registers described in Table 133.}

The 8 10G interfaces can be independently configured to have one or

four lanes active (quad SerDes), while the 16 2.5G interfaces always

have only one lane active (single SerDes).

With this combination of configuration parameters, the FM2112 can be

configured to support a mixture of 1G, 2.5G, and 10G Ethernet ports

within the constraint of 8 interfaces that support up to 10G in quad-

SerDes mode and 16 interfaces that support up to 2.5G in single-

SerDes mode, as well as any other 1-lane or 4-lane rate, within the

supported frequency range of the EPL interface.

For convenience of the board layout, lane reversal is supported, which

means that for each quad-SerDes port “Lane 0” to “Lane 3” is either

interpreted as an increasing order or a decreasing order. So that 1G

and 10G modes can be soft selectable on the same interface, the lane

reversal also affects whether “Lane 0” or “Lane 3” is used as the single

active SerDes to support 2.5G and 1G modes.

Figure 5 shows an example of an interface configured with one lane

active, connected to the first high-speed clock source.

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