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Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.2.11.3

3.2.12

3.3

Table Access Atomicity

Accesses to the MAC address table's 12 byte (3 word) MAC addresses

are atomic. A cache atomically refills a new entry when the lowest

order word of a table entry is read. And when the top word in the cache

is written, then the whole line is atomically written to the table.

Memory Integrity

{Described in registers Table 53 through Table 55}

The FM2112 tables are protected with parity. There are different

policies for parity errors depending on the severity of the outcome. No

parity errors are correctable in the hardware. The following is a

summary of the checking of parity errors and the actions on discovery

of a parity error:

• Frame memory

— Parity is checked indirectly by checking the RX and TX CRCs. The switch

generates an error if the RX CRC is good but the TX CRC is bad. The parity

error is counted. This parity error cannot lead to an illegal state.

— If the switch memory generates a parity error, the frame is transmitted with a

forced bad CRC whether the frame was cut-through or s-n-f.

• Scheduler Memory

— Parity errors are explicitly checked in the scheduler.

— Some scheduler parity errors are fatal and the chip should be reset

immediately. Others cause a memory leak which may not be necessary to fix

immediately.

• MAC address table

— Parity is explicitly checked in the MAC address Table.

— If a parity error is discovered, that MAC address line is treated as invalid, as if

the valid bit were set to zero.

—If the entry had been learned, then the error is self-correcting as the entry

will simply be relearned.

—However if the entry were statically configured, it must be rewritten by

software.

— A parity error interrupt is raised.

• VID/FID table

— Parity is explicitly checked in the VID/FID table.

— If a parity error is discovered the VID and FID entry for that VID TAG is treated

as invalid. This means that all frames on that VLAN are discarded until the

entry is rewritten by software.

— A parity error interrupt is raised.

Congestion Management

The FM2112 supports a rich set of congestion management features.

Figure 9 illustrates the flow frame data and control through the

FM2112.

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