FBFM2112F897CSLJLS 查看數據表（PDF） - Intel

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FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

1.1.3

• Multi-point Link-Ag extensions

• PAUSE flow control (802.3x)

• Inter-frame gap stretch (Rate Control)

• Intel® extensions to support complex topologies

and large-scale applications

Security

• MAC address security

• Port access control (802.1x)

Bridge Features

• 16K entry MAC address table

• Spanning Tree (802.1D, s, w)

• VLAN, priority (802.1Q, P)

• 4K VLAN table

• Link Aggregation (802.3ad)

• Duplex Flow Control (802.3x)

• All IEEE protocol traps

• User-defined monitoring and filtering rules

• RMON, and Intel® statisticsChip Performance

Test Features

• JTAG and boundary scan support

• Per-interface field loopback and BIST

Congestion Management

• Egress scheduling of 4 traffic classes

• Shared and private watermarks

• PWD (Priority Weighted Discard) on 16 priorities

• Priority regeneration

Control Features

• 32-bit standard CPU interface

• SPI EEPROM interface

• Standard LED interface

Physical

• 1.0W/0.5W (typ) per active 10G/2.5G interface

• Power scales linearly on activity

• 130 nm CMOS process technology

• 897-ball BGA package

Ethernet Interface Flexibility

The FM2112 contains 24 interfaces, 8 of which are quad SerDes

interfaces and can be independently configured to support one of the

following modes:

• 10G Ethernet: XAUI interface, with 10GBase-CX4 compliance (accomplished with

four SerDes pairs operating at 3.125 GHz, with 8b/10b encoding)

• 2.5G Ethernet: Pre-standard implementation (accomplished with a single SerDes

pair operating at 3.125 GHz, with 8b/10b encoding)

• 1G Ethernet: SGMII and 1000BASE-X compliance (accomplished with a single

SerDes pair operating at 1.25 GHz, with 8b/10b encoding)

• User-configurable mode: The FM2112 can support two input reference clocks, each

operating up to 400 MHz. Each of the device's 8 quad SerDes interfaces can

independently select one of the two reference clocks. Additionally, each interface

can be configured to have one or four SerDes pair(s) active. So, as an example,

given two input clocks of 312.5 MHz and 400 MHz, each interface can be

independently configured to support data rates of , 2.5 Gbps, 3.2 Gbps, 10 Gbps,

and 12.8 Gbps.

And 16 of which are single SerDes interfaces and can be independently

configured to support one of the following modes:

• 2.5G Ethernet: Pre-standard implementation (accomplished with a single SerDes

pair operating at 3.125 GHz, with 8b/10b encoding)

• 1G Ethernet: SGMII and 1000Base-CX compliance (accomplished with a single

SerDes pair operating at 1.25 GHz, with 8b/10b encoding)

• User-configurable mode: The FM2112 can support two input interface clocks, each

operating up to 4 GHz. Each of the device's 16 interfaces can independently select

one of the two reference clocks. Additionally, each interface can be configured to

have one or four SerDes pair(s) active. So, as an example, given two input clocks

9

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