Error detection mode functionality
STAP16DPPS05
7
Error detection mode functionality
7.1
Phase one: entering error detection mode
From the “normal mode” condition the device can switch to “error mode” by a logic
sequence on the OE/DM2 and LE/DM1 pins, as shown in the following table and
diagram:
Table 13: Entering error detection mode - truth table
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
H
L
Figure 18: Entering error detection mode - timing diagram
After these five CLK cycles, the device goes into the “error detection mode” and at the 6th
rising edge of the CLK, the SDI data are ready for sampling.
18/29
DocID024306 Rev 7